Verilog Rules and Examples I. Literals Verilog allows different ways to represent the same value in different bases. Syntax:<size>'<base><number> Example: 8’b10101111 // binary representation 8’hAF // hexadecimal representation {4’hA, 4’b1111} // combination of hex and binary {4’hA, {4{1’b1}}} // hex with repeated bits II. Module Declaration Each module should be placed in a separate file …